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| FSAR001 -- AC-DC Linear Regulator January 2011 FSAR001 AC-DC Linear Regulator Features High Output Voltage Accuracy: 2% Output Voltage: 5V Low Ground Current: < 2.0mA Ultra-Fast Line and Load Transient Response Hysteretic Thermal and Current-Limit Protections Over-Voltage and Under-Voltage Protections Ultra-Low Power Dissipation with No Load Universal Input Range: 80~265VRMS No Inductor Required Low Components and Cost Description FSAR001 is designed to replace capacitor-fed ("cap dropper") non-isolated power supplies, offering better high-power conversion performance and high-energy efficiency than a cap dropper solution. The appliance needs no inductor, uses few components, and offers lower cost. FSAR001 integrates a 600V high-power device, startup controller, voltage control circuit, synchronous circuit, low dropout regulator, over-temperature protector, overvoltage protector, under-voltage protector, and currentlimit circuit onto a monolithic IC. Applications Non-Isolation AC/DC Converter Home Appliance Ordering Information Part Number FSAR001BNY Operating Ambient Temperature Range -40C to +105C Output Voltage 5V Maximum Load 35mA Package DIP-8 Packing Method Tube (c) 2010 Fairchild Semiconductor Corporation FSAR001 * Rev. 1.0.0 www.fairchildsemi.com 1 FSAR001 -- AC-DC Linear Regulator Application Diagram Figure 1. Typical Application Internal Block Diagram Figure 2. Functional Block Diagram (c) 2010 Fairchild Semiconductor Corporation FSAR001 * Rev. 1.0.0 www.fairchildsemi.com 2 FSAR001 -- AC-DC Linear Regulator Marking Information ZXYTT AR001S TPM F - Fairchild Logo Z - Plant Code X - 1-Digit Year Code Y - 1-Digit Week Code TT - 2-Digit Die Run Code S: B: 5V VOUT T: Package Type (N=DIP) P - Y: Green Package M - Manufacture Flow Code Figure 3. Top Mark Pin Configuration DIP-8 GND VDD OUT DET 1 2 3 4 8 7 6 5 VIN VIN VIN VST Figure 4. DIP-8 Pin Configuration Pin Definitions Name VDD GND OUT DET VST VIN Pin # 2 1 3 4 5 6 7 8 Type Power Supply Ground Output Detect HV Start 600V Input Description Connect a 470F external capacitor to ground for generated VOUT+2.5V ~ VOUT+3.5V supply voltage. Ground Regulator output; fixed 5V output voltage Sin waveforms input connection. Connects to full-bridge output and provides synchronous signal. 500V power device startup connection. 600V power device input connection (c) 2010 Fairchild Semiconductor Corporation FSAR001 * Rev. 1.0.0 www.fairchildsemi.com 3 FSAR001 -- AC-DC Linear Regulator Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VIN VST VDET VDD VOUT PD JA TJ TSTG TL ESD Input Voltage of VIN Pin Input Voltage of VST Pin Input Voltage of DET Pin Input Voltage of VDD Pin Input Voltage of OUT Pin Power Dissipation (TA 50C) Parameter Min. Max. 600 500 7 30 30 1.15 95 Unit V V V V V W C/W C C C KV Thermal Resistance (Junction to Air) Operating Junction Temperature Storage Temperature Range Lead Temperature (Wave Soldering or IR, 10 Seconds) Human Body Model, JEDEC:JESD22-A114 Charged Device Model, JEDEC:JESD22-C101 All Pins Except HV Pin All Pins Except HV Pin (3) (3) -40 -55 +125 +150 260 6 2 Notes: 1. All voltage values, except differential voltages, are given with respect to the network ground terminal. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 3. ESD with HV pin CDM=1000V and HBM=500V. Recommended Operating Conditions Symbol VIN VST TA Parameter 600V High-Voltage Input 500V High-Voltage Startup Operating Ambient Temperature Min. Max. 600 500 Unit V V C -40 +105 Note: 4. For proper operation. (c) 2010 Fairchild Semiconductor Corporation FSAR001 * Rev. 1.0.0 www.fairchildsemi.com 4 FSAR001 -- AC-DC Linear Regulator Electrical Characteristics VIN=open, VDD=VOUT+1 V, CVDD=470 F/ 25 V, COUT=10 F/ 16 V, IOUT=1 mA, TA=25C, unless otherwise noted. Symbol VDD Section VTH-ON VTH-OFF IDD-ST IDD-OP VDD-OVP tVDD-OVP VIN Section VVIN ST Section IST IST-LC Parameter Turn-on Threshold Voltage (VOUT=5V) Turn-off Voltage (VOUT=5V) Startup Current of VDD Pin Operating Supply Current Threshold of VDD OVP Time Delay of VDD OVP Supply Voltage Conditions Min. Typ. Max. Unit VDD Pin VDD Pin VDD Pin IOUT=1mA 9 3 1.0 0.8 10 4 10 1.5 1.0 1.5 11 5 30 2.0 VOUT+4.0 1.2 V V A mA V V s VOUT+3.0 VOUT+3.5 VDD-OVPHYS Threshold of VDD OVP Hysteresis 600 VAC=90V (VDC=120V), VDD=10F OFF+1V V Supply Current from ST Pin Supply Current After Startup 2.50 3.75 1 5.00 20 mA A HV=500V, VDD=VDD- DET Section VDET_MAX Turn-Off Synchronous Voltage 0.90 0.08 0.08 0.08 0.95 0.10 0.14 0.14 0.1 -10.0 -2 IOUT=1mA to Maximum VDD=VOUT+3V IOUT=35mA Output Current = Maximum Load VOUT=0%~90% COUT=1F f= 50Hz, COUT=10F, IOUT =35mA f =100Hz, COUT=10F, IOUT =35mA (6) (6) 1.00 0.12 0.20 0.20 V V V V A VDET_MAXHYS Turn-Off Synchronous Voltage Hysteresis VDET_MIN Turn-On Synchronous Voltage VDET_MINHYS Turn-Off Synchronous Voltage Hysteresis IDET UVPVout VACC LR ILIM VDrop IG tDOUT-ST DET Current Output Pin Under-Voltage Protection Output Voltage Accuracy Load Regulation Current Limit Dropout Voltage (VOUT=5V) Ground Pin Current (5) VOUT Section -12.5 -15.0 2 2 0.2 140 0.4 1.5 40 50 170 0.5 2.0 60 % % % %/V mA V mA s -2 -0.2 110 0.3 VOUT (VIN) Line Regulation dVOUT/dVIN Output Voltage Rising Time (VOUT=12V) VDD to VOUT Ripple Rejection (6) PSRR TOTP THYS 60 150 TOTP-40 dB C C Protection Junction Temperature Restart Junction Temperature Notes: 5. For VDrop=1V of VOUT=3.3V version, the test condition is modified to VDD=VOUT+1.5V. 6. Guaranteed by design. (c) 2010 Fairchild Semiconductor Corporation FSAR001 * Rev. 1.0.0 www.fairchildsemi.com 5 FSAR001 -- AC-DC Linear Regulator Typical Performance Characteristics VAC = 264V/50Hz, VOUT = 5V, IOUT=35mA~40mA, CVDD = 470F, COUT = 10F, TA = 25, unless otherwise noted. Figure 5. VOUT Pin Under-Voltage Protection Figure 6. Current Limit 100 COUT ESR (ohm) 10 Stable Region 1 0 10 20 30 40 50 Load Current (mA) Figure 7. Load transient Figure 8. Region of Stable COUT ESR vs. Load Current Figure 9. Ground Pin Current vs. Load Current Figure 10. Operating Supply Current vs. Temperature (c) 2010 Fairchild Semiconductor Corporation FSAR001 * Rev. 1.0.0 www.fairchildsemi.com 6 FSAR001 -- AC-DC Linear Regulator Typical Performance Characteristics (Continued) Figure 11. Turn-On Threshold Voltage vs. Temperature Figure 12. Turn-Off Threshold Voltage vs. Temperature Figure 13. Threshold of VDD OVP HIGH vs. Temperature Figure 14. Threshold of VDD OVP LOW vs. Temperature Figure 15. Output Voltage vs. Temperature Figure 16. Output Voltage vs. Output Load (c) 2010 Fairchild Semiconductor Corporation FSAR001 * Rev. 1.0.0 www.fairchildsemi.com 7 FSAR001 -- AC-DC Linear Regulator Functional Description The FSAR001 is a compact, inductor-free, and highly monolithic AC/DC linear converter housed in 8-lead DIP packages and designed for non-isolated AC/DC converter and home appliances. The FSAR001 provides universal AC voltage input from 80VRMS to 265VRMS and fixed-DC output voltage with current limiter for the non-isolated AC/DC converter operating safety and stability. The FSAR001 integrates many protection functions, including output current limiter (ILIMIT), output under-voltage protection (UVP), over-temperature protector (OTP), VDD over-voltage protection (OVP), and AC synchronous signal detect function (VDET). As the FSAR001 operates in a typical application, the startup current flows through the startup pin (VST) and charges VDD capacitor. When the voltage of VDD is larger than VTH_ON, the FSAR001 is turned on. After one AC synchronous signal, the LDO is turned on and creates output voltage (VOUT). At steady state, the energy of VDD capacitor decreases because of the chip operation and load power dissipation. The behavior is shown in Figure 17 and the energy is recharged during conduction angle interval (settled by R3 and R4) and under OVP function limitation (VDD-OVPH). With a view to increasing LDO efficiency and system stability, FSAR001 sets the VDD OVP voltage at 8.5V for 5V LDO regulator. The VDD capacitor recovery angle controls below 50VRMS settled by AC synchronous signal (DET sense voltage), detailed in the following sections. VIN Max Max OUT Pin Under-Voltage Protection When the output power is larger than the maximum handling power of FSAR001, the condition causes the output voltage to drop. Until the output voltage is less than output nominal voltage -12% (5V - 0.625V = 4.375V), the UVP function disables the LDO stage and waits until the next AC synchronous signal to restart the FSAR001 automatically. Current Limit The FSAR001 includes a current limiter (ILIMIT) for safe LDO operation. The limiter monitors the loading current and directly controls the output delivery current of LDO. The typical limited current set is 140mA to avoid the output shorted to ground for an indefinite amount of time without damaging the part. At over-current operation, the ILIMIT function limits the maximum output current and causes the unregulated output voltage to drop until the UVP function occurs. Over-Temperature Protection The FSAR001 operates in highly converting ratio. The thermal energy of FSAR001 is generated by the inner converting power of the MOSFET. When the junction temperature (TJ) exceeds 150C, the OTP function disables LDO stage and waits for the next AC synchronous signal to restart. The over-temperature hysteresis range is 40C. After startup, the OTP function monitors the junction temperature. When junction temperature decreases to the (TOTP-THYS), the OTP function enables the signal and allows LDO turn on. If not, OTP function keeps the output function disabled and continuously monitors the junction temperature. The OTP function is designed to protect against abnormal conditions and over-power operation. Conduction angle (set by R3&R4) IIN DET Pin Selection The DET pin connects to the commutated AC bus. It sinks commutated AC voltage waveform used to provide the AC synchronous signal and to set the VDD capacitor recovery conduction angle. For synchronous signal function, the AC synchronous signal used to enable output voltage of the LDO and to trigger the output stage protection with UVP and OTP. To limit the recovery-conduction angle of the VDD capacitor, the DET pin sense voltage (VDET) is set between 0.14V ~0.95V. During the sense-voltage range of the DET pin, the VDD capacitor can be charged by the power MOSFET until the OVP function is operating in every synchronous cycle. As shown in Figure 18, the DET pin sense voltage limits the charge time of t0~t1 and t2~ts/2 settled by R3 and R4. The maximum commutated input voltage of FSAR001 can be determined by the following equation with the maximum DET sense voltage defined: VOUT CVDDmax LDO Load VDD(capacitance) Figure 17. Operating Principle Startup Current During FSAR001 startup, the startup current through the rectifier and VST pin charges the VDD capacitor with maximum start current of VST pin of 3.75mA and the synchronous current controlled by R3 (1M) and R4 (13k), shown in Figure 1. The FSAR001 remains off until the VDD voltage is larger than VTH-ON and the output voltage is created at the same time. After the FSAR001 turns on, the VST function is disabled by the control loop. The major energy path changes from VST pin from the inner power MOSFET MV (VIN). (c) 2010 Fairchild Semiconductor Corporation FSAR001 * Rev. 1.0.0 www.fairchildsemi.com 8 FSAR001 -- AC-DC Linear Regulator Functional Description (Continued) VDET ,max = VDET ,min R4 x Vac R3 + R 4 R4 = x Vac R3 + R 4 dissipation in the first stage. During the power MOSFET turn-on, the current provided by the commutated AC voltage is used to supply the loads and to charge the VDD capacitor. In this way, when the power MOSFET switches off, the loads receive the required currents by the capacitor discharge. For this reason, it is important to properly set the conduction angle. For the VDD capacitor selection, during conduction angle interval; the energy is drawn from commutated AC bus, which not only provides the output requirement but also recharges the VDD capacitor to OVP level. Outside of conduction angle, the VDD capacitor supplies the whole system requirement. The VDD capacitor can be reduced by maximum loading power. The capacitor is evaluated by Equation 2; the selection chart is shown in Figure 19. t0 t1 t2 Ts/2 Ts EQ 1 VIN VINpeak VINDET t IIN a. CVDD = I LOAD x 10m , (unit = F ) 1 EQ 2 600 b. t VDD capacitor (uF 500 400 300 200 100 0 0 10 20 30 40 50 Figure 18. Typical Waveforms VDD Pin Over-Voltage Protection After startup, FSAR001 turns on the OVP function. During conduction angle interval, the VDD voltage has two kinds of behavior. One is that if the VDD capacitor recharges to OVP trigger point (8.5V for 5V version), the FSAR001 turns off the power MOSFET to limit the maximum VDD voltage. The other is that if the voltage of VDD cannot recharge to the OVP level during the conduction interval, the power MOSFET is turned off by AC synchronous signal and continuously recharges VDD capacitor at next duration. Using this technique, energy is drawn from the AC mains only during the low-voltage portions of each positive half cycle, reducing the Load Current (mA) Figure 19. VDD Capacitor vs. Output Current (c) 2010 Fairchild Semiconductor Corporation FSAR001 * Rev. 1.0.0 www.fairchildsemi.com 9 FSAR001 -- AC-DC Linear Regulator Applications Information Figure 20. Application Circuit BOM Designator F1 C1 C2 C3 C4 D1 Part Type FUSE 4A/250V 0.01F/50V 470F/25V 10F/25V 0.01F/50V 1N4007 Designator D2 R1 R2 R3 R4 Part Type 1N4007 R 1M 1/4W R 10 2W R 1K 1/4W R 13K 1/4W (c) 2010 Fairchild Semiconductor Corporation FSAR001 * Rev. 1.0.0 www.fairchildsemi.com 10 FSAR001 -- AC-DC Linear Regulator Physical Dimensions 9.83 9.00 6.67 6.096 8.255 7.61 5.08 MAX 3.683 3.20 7.62 0.33 MIN (0.56) 2.54 3.60 3.00 0.56 0.355 1.65 1.27 7.62 0.356 0.20 9.957 7.87 NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-001 VARIATION BA B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS. D) DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994 E) DRAWING FILENAME AND REVSION: MKT-N08FREV2. Figure 21. 8-Pin, DIP-8 Package Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. (c) 2010 Fairchild Semiconductor Corporation FSAR001 * Rev. 1.0.0 www.fairchildsemi.com 11 FSAR001 -- AC-DC Linear Regulator (c) 2010 Fairchild Semiconductor Corporation FSAR001 * Rev. 1.0.0 www.fairchildsemi.com 12 |
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